NJU7505 -1- ver.2004-06-04 band pass filter for audio spectrum analyzer display ! general description ! package outline the NJU7505 is a band pass filter for audio spectrum analyzer display. it consists of high and low band pass filters, cr oscillation circuit, control circuit and dc transfer circuit. each band pass filter using the switched capacitor filter technology operates at the shared time by 5 bands which filter constant is switched by the internal clock. therefore, the audio signal shared of 5 bands is output from a serial output terminal. the 10 bands version using the double by the cascade connection is prepared. ! features ! pin configuration " bpf for the audio spectrum analyzer display of the 5 bands " 10 bands extension is available by the cascade connection (version of a: for 5-band application by the single) (version of b: for 10-band application by the double) " bpf using the switched capacitor filter technology " cr oscillation circuit on chip (external clock input is available) " power-on initialization circuit on chip (external reset input is available) " c-mos technology " package outline dip8, dmp8 ! block diagram NJU7505xd NJU7505xm a in a out v dd v ss v dd a gnd v ss h l osc1 osc2 rst/clko rd audi o sig n al control signa cr ock sig nal power-on initialize cont rol circuit osc f osc f osc/16 f osc/4 bpf high band high band peak detector r h r l i l i h lpf input buf bpf low band low band peak detector lev el shif ter & out put buf 1 2 3 4 5 6 7 8 osc1 osc2 rst/clko rd v dd a in a out v ss
NJU7505 - 2 - ver.2004-06-04 ! terminal description no. symbol function 1 2 osc1 osc2 external resistor connecting terminal. external resistor connecting terminal or external clock input terminal. 3 rst/clko both as reset input terminal and the clock of (2/3)*fosc output terminal. 4 rd trigger signal for reading-out the a out of each band output terminal. 5 8 v ss v dd gnd 0v positive power supply +5.0 v 6 a out peak voltage of each band output terminal. 7 a in audio signal input terminal. ! version lineup and peak frequency the NJU7505 prepares two version of a and b which are different of the peak frequency of each bands. the version of a is recommended for the 5 bands application using the single and the version of b is recommended for the 10 bands using the double by the cascade connection, however, the version of a can be used for the 10 bands using the double and the version of b can be used for the 5 bands using the single. peak frequency ( hz ) using the single using the double band version of a version of b version of a version of b f1a 12k 18k 12k 18k f1b - - 8k 12k f2a 3.5k 5.3k 3.5k 5.3k f2b - - 2.3k 3.5k f3a 1k 1.5k 1k 1.5k f3b - - 670 1k f4a 250 375 250 375 f4b - - 165 250 f5a 63 95 63 95 f5b - - 42 * 63 note 1) the bands of f1a, f2a, ... f5a correspond to the master side and the bands of f1b, f2b, ... f5b correspond to the slave side at the cascade connection of the double. note 2) it may not be output along the expectation at the peak frequency of * marking, since the sampling time is not enough. the example of using the single the example of using the double osc1 osc2 f os c NJU7505 a out f 1a to f5a osc1 2/3 * f osc NJU7505 master a out f 1a to f5a f os c rst/clko NJU7505 slave a out osc1 osc2 f 1 b t o f 5 b
NJU7505 -3- ver.2004-06-04 ! functional description # interface to external controller the example of the interface between the NJU7505 and the external controller is shown below; (1) example of the interface to the external controller ( using the single ) after the rst signal from the external controller is input and then the internal circuit is initialized, each band data is output as shown below timing chart; since the rd signal is output before each band is switched, the external controller is to count the number of the rd signal and is to recognize the status of the band and is to read the output data from the a out terminal through the external a/d converter. the output type of the external controller connected to the rst/clko terminal as the rst input should be the n-channel and open-drain type or the diode should be connected between the rst/clko terminal and the output terminal of the external controller, so that the voltage of the rst/clko terminal is not gotten over the v ss level. since the rd signal is output before 248/f osc of each band switched, the output data should be read out within the limited time as shown right; if the rst signal which pulse width is more than 4/f osc is input, the internal circuit is initialized and the data of f1 band is output from the a out terminal after 52/f osc of the rise edge of the rst signal. NJU7505 a in a out os c1 os c2 f os c v ss rd a / d converter rst/clko c om a out rd rst f1 f2 f3 f5 f1 f2 f4 f3 f1 f1 f2 f3 f1 f2 f3 f5 f1 f2 f4 f3 f1 f2 3*2 / fosc 14 a out 248 / f osc rd 8 / fosc available period of read-out a out fn rst 4/ fosc[min] 52/ f osc f1
NJU7505 - 4 - ver.2004-06-04 (2) example of the interface to the external controller (using the double) the 10 bands application is available using the cascade connection of the double NJU7505 as shown blow. after the rst signals from the external controller are input to each of the master and the slave of the NJU7505 and then each internal circuit is initialized, each band data is output as shown below timing chart; since the rd signals are output from the master and the slave before each band is switched, the external controller is to count the number of the rd signals and is to recognize the status of the band and is to read the output data from each a out terminals through the external a/d converter. the master clock for the slave is provided with the output signal from the rst/clko terminal of the master. the master clock for the slave is stopped when the rst signal is input from the external controller to the master, so that the rst/clko terminal of the master is used both as the rst input of the master and the master clock for the slave. the output type of the external controller connected to each rst/clko terminal as the rst input should be the n-channel and open-drain type or the diode's should be connected between each rst/clko terminal and the output terminals of the external controller, so that the voltage of each rst/clko terminal is not gotten over the v ss level. rst/clko rst/clko a/d converter NJU7505 slave NJU7505 ma s te r a out a in osc1 osc2 osc2 a out a in v ss rd rd com ma s t e r slave a out rd rst f1 f2 f3 f5 f1 f2 f4 f3 f1 f1 f2 f1 f2 f3 f5 f1 f2 f4 f3 f1 f2 3*2 / fosc 14 f3 f2 f3 f1 3*2 / fosc * 3/2 14 a out rd rst f5 f1 f2 f3 f1 f1 f5 f3 f1 f2 f2 f2 f3 f4 f3 f4 f1 f1 f2
NJU7505 -5- ver.2004-06-04 since each rd signal of the master and the slave is output before 248/f osc (248/f osc *3/2) of each band switched, the output data should be read out within the limited time as shown right; * the "( )" is corresponded to the slave. if the rst signal which pulse width is more than 4/f osc is input to the master, the internal circuit is initialized and the data of f1 band is output from the a out terminal of the master after 52/f osc of the rise edge of the rst signal. the rst signal for the slave should be set to "l" level while the rst signal for the master is "l" level and should keep "l" level more than 6/f osc . so the slave operates as same as the master after 78/f osc of the rise edge of the rst signal for the slave. a out 248 / f osc (248/ fosc*3/2) rd 8 / fosc (8/ fosc*3/2) available period of read-out a out (master) rst (master) rst (slave) a out (slave) fn f1 4/fosc[min] 52/ fsoc 6/fosc[min] 78/ f soc fn? f1?
NJU7505 - 6 - ver.2004-06-04 ! absolute maximum ratings (ta=25c) parameter symbol ratings unit note supply voltage v dd -0.3 to +7 v v in -0.3 to v dd +0.3 7 input voltage v io -0.3 to 0 v 5, 8 output voltage v out -0.3 to v dd +0.3 v power dissipation p d 500(dip), 300(dmp) mw operating temperature t opr -30 to 85 c storage temperature t stg -55 to 125 c note 3) if the ic are used on condition above the absolute maximum ratings, the ic may be destroyed. using the ic within electric characteristic conditions will cause malfunction and poor reliability. note 4) all voltage values are specified as v ss = 0v. note 5) when the voltage of the rst/clko terminal is gotten over the v ss level, the diode should be connected between the rst/clko terminal and the external. note 6) decoupling capacitor should be connected between the v dd terminal and the v ss due to the stabilization of the operation. note 7) applied to the a in or the osc2 terminals. note 8) applied to the rst/clko terminal. ! electrical characteristics dc characteristics (v dd =5v, v ss = 0v, ta=25c) parameter symbol condititons min typ max unit note operating voltage v dd 4.5 5.0 6.0 v operating current i dd v dd terminal - 6.0 12 ma i il1 v il1 =0v -0.1 -0.05 -0.033 input leak current 1 i ih1 a in terminal v ih1 =5v 0.033 0.05 0.1 ma input leak current 2 i il2 rst/clko terminal v ih2 =0v -0.2 -0.1 -0.05 ma v ilc 0 - 1.5 external clock input voltage v ihc osc2 terminal 3.5 - 5.0 v v ol1 i ol1 =100a 0 - 0.5 output voltage 1 v oh1 rd terminal i oh1 =-100a 4.5 - 5.0 v v ol2 i ol1 =100a 0 - 0.5 output voltage 2 v oh2 rst/clko terminal i oh1 =-5a 4.25 4.5 4.75 v output offset voltage v os a out terminal a in :open - - 300 mv - 26.0 - db 9,10,11 bpf output voltage v out a out terminal sine wave input f in =f1 to f5 v in =200mv p-p 3.5 - - v 9,10 note 9) this specification is tested on condition of f clk =400khz (the external clock is input to the osc2 terminal through the capacitor for ac coupling. note 10) each input frequency of f1 to f5 is referred to the table of the " version lineup and peak frequency ". note 11) this specification is calculated from " v out / v in ".
NJU7505 -7- ver.2004-06-04 ! ac characteristics ( v dd =4.5 to 6.0v, v ss =0v, ta=25c) parameter symbol conditions min typ max unit note oscillation clock freq f osc rst/clko terminal v dd =5v 360 400 440 khz 12 external clock frequency f clk rst/clko terminal v ilc =0v v ihc =v dd 400 800 khz 13 master 8/f osc 8/f clk rd pulse width t pwrd rd terminal slave 12/f os c 12/f clk s 14 master 4/f osc 4/f clk rst pulse width t pwrs rst/clko terminal slave 6/f osc 6/f clk s 15 rst rise/fall time tr, tf rst/clko terminal 100 na 15 note 12) the example for the cr oscillation note 13) the example for the external clock input note 14) the output wave form of the rd terminal. note 15) the input wave form of the rst terminal. osc1 osc2 v ss rt ct osc1 osc2 oscillator open 0.8v dd t pwrd 0.8v dd 0.8v dd 0.8v dd 0.2v dd 0.2v dd t pwrs tf tr *the oscillation clock frequency is calculated from the output frequency of the rst/clko terminal by 3/2. rt: 13k ? ( 2%) ct: 220pf( 5%) the input signal for the osc2 terminal should be the condition of the pulse of duty50% 10%. * the oscillation clock frequency is calculated from the output frequency of the rst/clko terminal by 3/2.
NJU7505 - 8 - ver.2004-06-04 ! application circuit (1) *1 ) the capacitor for ac coupling connected to the a in terminal should be needed. *2 ) connecting the attenuator, the dynamic range of the display can be changed. *3 ) when the voltage of the output terminal of the com gets over the v ss level, the diode should be connected between the rst/clko terminal and the output of the com. lch a udio in a udio out a udio in a udio out reso na nce circuit nju7305 reso na nce circuit a tt. *2 *1 a in osc1 osc2 NJU7505 13k 220pf v ss rd rst/clko *3 a out a/d display driver display com rc h
NJU7505 -9- ver.2004-06-04 ! application circuit (2) *1 ) the capacitor for ac coupling connected to the a in terminal should be needed. *2 ) connecting the attenuator, the dynamic range of the display can be changed. *3 ) when the voltage of the output terminal of the com gets over the v ss level, the diode should be connected between the rst/clko terminal and the output of the com. lch a udio in a udio out audio in a udio out resonance circuit nju7305 resonance circuit att. *2 *1 osc1 osc2 NJU7505 13k 220pf v ss rd rst/clko a out a/d display driver display com *2 att. a in a in rst/clko osc2 rd NJU7505 a out *3 *3 a/d rc h [caution] the specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. the application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights.
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